In digital circuit design, it is sometimes useful to have a free-running clock oscillator that can provide a higher frequency clock than the system clock. FIG. 1 is a block diagram illustrating a conventional clock oscillator design. In this example, a ring oscillator 100 includes several gain stages with delay (102–108) and an inverter 110. The overall phase shift between input 112 and output 114 is 360 degrees. The circuit has an oscillation frequency that corresponds to the cumulative delay.
To guarantee clock compatibility with conventional logic circuits, the clock signal provided by the oscillator should have good precision. Since the frequency and waveform of the ring oscillator may vary due to variations in the manufacturing process or changes in the operating temperature of the circuit, ring oscillators are generally not used in digital integrated circuit (IC) design. Ring oscillators are typically avoided in the designs of semi-custom digital ICs such as gate-array application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), because these circuits require the clock signals that meet certain minimum voltage levels as well as pulse widths for the flip-flops used in the circuits. It would be desirable to have a clock oscillator design that could meet the specifications of the circuits. It would also be useful if the clock signal could consistently meet its requirements despite variations in the process and operating conditions.